A memory cell array, such as a dynamic random access memory (DRAM) can be arranged in a row-column format by rows or word lines (WL) and columns or bit lines (BL). The memory cell array can be segmented by grouping the memory cells into areas of the memory array, and these memory areas can be addressed logically and/or physically. For example, a plurality of rows is combined together to form a row group, which can be addressed separately from another row group of a plurality of rows contained within the memory array. These groups of rows are commonly referred to as memory banks. A group of memory cells along a column can be segmented or separately addressed from another group of memory cells along the same column or column select line (CSL). These groups of memory cells within a column or column select line are referred to as column segments or column select line (CSL) segments.
Each memory cell is structured for storing digital information in the form of a “1” or a “0” bit. To write (i.e., store) a bit into a memory cell, a memory address having portions identifying the cell's row (the “row address”) and column (the “column address”) is provided to address circuitry in the semiconductor memory to activate the memory cell, and the bit is then supplied to the memory cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the memory cell is again activated using the cell's memory address, and the bit is then output from the memory cell.
When memory cells are arranged in groups of rows, which are typically called rows groups or blocks, the binary memory address can include a row group or block address. For example, if the memory contains a plurality of memory cells arranged together in a block or row group, the address can include bits identifying the block or row group in the memory cell array to be accessed.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing or faulty memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing or bad memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in a redundant row or redundant word line (RWL), a redundant column or BL, and/or a redundant column select line segment (RCSLS).
When a redundant row is used to repair semiconductor memory containing a failing memory cell, the failing cell's row address is permanently stored (typically in predecoded form) within the semiconductor device on which the semiconductor memory is fabricated by programming a nonvolatile element (e.g., a group of fuses, antifuses, or FLASH memory cells) on the semiconductor device. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a row address that corresponds to the row address stored in the semiconductor device, redundant circuitry in the semiconductor device causes a redundant memory cell in the redundant row to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell's row has the same row address, every cell in the failing cell's row, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a column needs to be repaired in the semiconductor memory, the failing cell column is permanently stored (typically in predecoded form) on the semiconductor device by programming a nonvolatile element on the semiconductor device. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a column address that corresponds to the column address stored within the semiconductor device, redundant circuitry in the semiconductor device causes a redundant memory cell in the redundant column to be accessed instead of the memory cell data identified by the received memory address. As every memory cell in the failing memory cell's column has the same column address, every memory cell in the failing memory cell's column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
The current redundancy schemes select the column select line repair region during row activation based on the row group address. If an addressed row needs to be replaced (i.e., it contains a bad or faulty memory cell), it can be replaced with a row within the same block or row group (i.e., intra-group repair) or outside the block or group (i.e., inter-group repair). If the column select line in the original row segment needs repair, a corresponding or identical column select line repair is made in the row group into which the defective row is replaced. The column select line replacement occurs whether or not the column select line in the new or redundant row group is defective. Alternatively, it is possible that the column select line in the original row group is operative while the column select line in the new or redundant row group is defective. Since the column select line repair region is determined by the row address of the row requiring repair, the defective column select line in the new row or redundant group will not be repaired, and therefore a fault will occur. This arrangement limits the repair options. For such reasons, the current redundancy scheme limits flexibility in repair.
As a result of the above-described replacement scheme, operative memory cells can be unnecessarily replaced, thereby reducing overall memory yield during production.